Hardware-in-the-loop test configurations require real-time execution speeds from their simulation components for best results. Slower-than-real-time simulations can degrade test result accuracy, completely invalidate a test, and potentially even damage the hardware component being tested; however, some simulations required for testing cannot be guaranteed to run in real time or faster-than-real-time. Thus, we developed a method to allow slower-than-real-time simulations to be used in HIL test setups. Input signals to the simulation are predicted using a simplified hardware model. The simulation uses these predicted values to run “ahead” of the hardware component in time. When a sufficient time margin is obtained, depending on the actual execution speed of the simulation, the hardware component is connected to the stored simulation results computed using the predicted inputs from the hardware model and the test commences. Simulation results are supplied to the hardware component in real time, for as long as the simulation time margin remains. A case study using a small modular reactor simulation code shows that using this method allows test lengths at least 350% longer and simulation error of 0.6% compared to 36%.