We propose a design and verification process for a hardware-resource-efficient FPGA-based functional safety controller. In order to reduce the hardware resources consumed by the NPP application, we developed a resource-sharing calculation architecture on the FPGA. Our designed FPGA-based controller utilizing our developed architecture is hard-wired, but can operate another function by replacing contents in the calculation control memory. Thus, our developed controller achieves both safety and flexibility. In addition, a data conversion tool from NPP application to calculation control data for our developed architecture is also developed. In the verification step, output data from our developed tool is verified by a process where that calculation control data is reversely-converted to the NPP application and checked whether it is equivalent with the original NPP application by the logical equivalence verification method. Our verification process makes it possible to apply formal verification method and achieve the SIL 4 compliant verification process for the FPGA-based controller for Class 1 I&C systems . Our proposed design and verification process was assessed by TÜV Rheinland and accepted as SIL 4 compliant.